![]() Long, W., Ou, H., Kuo, J., Chin, K.: Dual-material gate (DMG) field effect transistor. In: Devices for Integrated Circuit (DevIC) IEEE, pp. K.: Surface potential based analytical modeling of graded channel strained high-k gate stack dual-material double gate MOSFET. Yu, B., Yuan, Y., Song, J., Taur, Y.: A two-dimensional analytical solution for Short-Channel effects in nanowire MOSFETs. In: Devices for Integrated Circuit (DevIC), pp. Junctionless thin film transistor (JLTFT)īhushan, S., Kumar, A., Gola, D., Tiwari, P.K.: An analytical subthreshold current model of short-channel symmetrical double gate-all-around (DGAA) field-effect-transistors. ![]() The proposed IGZO-based JLTFT device, which is designed using SOI technology on HfO 2 dielectric, will make it high performance and cost-effective device for low power applications. It shows 21.9% improvement in Subthreshold Swing (SS) as compared to device present in reference work. The proposed device has a very high I ON/ I OFF = 2.14 × 10 7 and a low subthreshold swing = 72.67 mV/decade ensuring a better current driving capability and high speed of operation. The geometry of the device structure has been successfully optimized by using vertical gate stacking technique and making variations in the channel and buried oxide layer thickness. The proposed device structure is analyzed using Silvaco TCAD ATLAS™ 2-D simulator. High dielectric constant ( k) material HfO 2 is used as gate insulator and buried oxide layer. This paper proposed design and analysis of an Indium Gallium Zinc Oxide (IGZO)-based Junctionless Thin Film Transistors (JLTFT), using 20 nm Silicon On Insulator (SOI) technology. ![]()
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